The present invention relates generally to a semiconductor memory device, and more specifically to a structure of electrically programmable read-only memory cells, which is suitable for use as ROM spare cells provided with redundant structure. Further, the present invention relates to redundancy signature for a ROM of redundant structure.
As electrically programmable read-only memory cells, there have been proposed several types of memory cells as follows: transistors are combined with fuses, respectively; data are programmed by destructing diodes or oxide films, respectively; etc. Above all, memory cells including fuses, writing transistors, and reading transistors have been widely and preferably used as spare cells in the redundancy circuit (for detective cell relief) of a mask ROM, because the manufacturing process is simple, the reliability is high, and the program is easy to prepare. FIG. 1 shows a circuit diagram of the memory cells.
In the prior-art circuit shown in FIG. 1, however, since a single memory cell 1 is composed of three elements of a writing transistor 3, a reading transistor 5, and a fuse 7, the area occupied by a single cell 1 is relatively large. Therefore, when the memory cells are used as spare cells in the redundancy circuit of a mask ROM, there exists a problem in that the chip size increases as the number of spare cells is increased to improve the effect of defective cell relief.
To overcome this problem, it may be considered that a single transistor is used in common as the writing and reading transistors. However, where the transistors are simply arranged as described above, since bit lines 9 are directly connected to a pad 11 to which a high voltage is applied, there arises another problem in that parasitic capacitances of the high-voltage applying pad 11 and other elements (e.g. probe) for applying high voltage to the pad are directly connected to the bit lines 9, with the result that the operating speed is reduced.